As new generations of electrical consumer products are developed, there is a growing need for miniaturization of components, integration of several system functions within a component, and improvement of component performance and reliability. For example, thin semiconductor packages have enabled the implementation of consumer products with lower profiles such as ultra-thin cell phones, displays, and laptop computers. Similarly, integration of electronic components within a single package has increased the performance cell phones and computers.
Advances in semiconductor package technology continue to enable miniaturization, greater system integration, and greater reliability while reducing the overall cost of consumer devices. These trends have resulted in a requirement for increased circuit density and have led to the development of multi-chip packages incorporating more than one semiconductor die.
A single-chip package provides mechanical support for an individual semiconductor die and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry within separate semiconductor dies.
Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of a PCB substrate onto which a set of separate semiconductor dies is directly attached. The reliable implementation of multi-chip packages may be impacted when several semiconductor dies are arranged vertically or horizontally in the package because one critical defect induces a complete package failure, which is costly.
Moreover, vertically stacked semiconductor dies in typical multi-chip packages can present problems beyond those of horizontally arranged integrated circuit packages, further complicating the manufacturing process. It is more difficult to test and thus determine the actual failure mode of the individual semiconductor die. Moreover individual semiconductor dies are often damaged during assembly or testing, complicating the manufacturing process and increasing costs, since a single semiconductor die or interconnect defect results in the failure of the entire multi-chip package.
Thus, a need still remains for a means for creating multi-chip package systems incorporating several semiconductor dies that can be assembled using pre-tested modules, also known as Known Good Packages (KGP). Moreover, these package modules must also have a robust design and construction to withstand stresses and temperature cycles used for the assembly of the multi-chip package.
In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.